Speaker:
Rafal Szarecki, Juniper Networks

In this talk I describe buffering architecture, starting form shared memory used in devices build around single centralized switch (SoC) and then focusing on distributed architectures more common used in today's routers. The OQ, IQ, VoQ and CIOQ buffering strategies are described and explained, following by strengths and limitation of each. Finally impact of chosen architecture on ASIC design would be briefly evaluated. The intention is to provide knowledge about foundation of routers system architecture, that could be useful to troubleshoot certain network events that manifest as packet loss somwhere inside router. The whole talk is based on theoretical models, not related to any specific vendor's product. However each product follows (w/ some deviation) one of discussed model - so knowledge provided would be relevant to operation of this product and understand their internal as well as deviation in behavior of different product when exposed to the same traffic.